1. Field of the Invention
The present invention relates generally to memory devices and systems which use memory devices and, more particularly, to the structure and operation of a memory device that uses relaxed write timing.
2. Description of the Related Art
Microprocessor-controlled circuits are used in a wide variety of applications. Such applications include personal computers, control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device coupled to the microprocessor. Not only does the microprocessor access a memory device to retrieve the program instructions, it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a wide variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particular function. One common type of memory device is known as a random access memory (RAM). As the name implies, any memory location in a RAM may be accessed individually to store information or to read information. As a further advantage, the memory cells used in most RAMs are capable of handling millions of write, read, and erase cycles, commonly referred to as programming cycles, without failure.
The two most common and versatile types of RAMs are the dynamic RAM (DRAM) and the static RAM (SRAM). A memory cell of a typical DRAM is formed by a single capacitor and a single transistor. Digital information is stored in the form of a charge on the capacitor, and the transistor permits the capacitor to be accessed for charge storage (writing) or charge detection (reading). Because of this simple memory cell configuration, DRAM memory cells may be densely packed together to form single chip memories having extremely high capacities, currently approaching one gigabyte. Disadvantageously, however, the charge on the memory capacitors tends to diminish rather quickly, requiring periodic refresh cycles. Also, because the stored charge is quite small, relatively complex signal detection and amplification circuitry is used to access the memory cells, thus providing somewhat slower access times than comparable SRAMs.
The primary advantages of SRAMs as compared to DRAMs are high speed and ease of use. To understand the advantages and disadvantages, it should first be understood that a typical SRAM memory cell includes a four transistor-latch that stores information and two transistors that permit access for reading or writing information in the latch. The main disadvantage relates to the size of the memory cell required by the six transistors. Because of their size, SRAM memory cells cannot be packed as densely as DRAM memory cells. Therefore, the capacity of a single chip SRAM has not yet, and will probably never, reach the capacity of a single chip DRAM.
However, the superior performance of SRAMs derives from the larger signal stored in the latch and the absence of a need to refresh the stored information. As a result, the signal detection and amplification circuitry used in SRAMs is far simplier, easier to use, and offers higher access speeds. In regard to the access speeds, most current SRAM designs typically exhibit access times of a few nanoseconds to a few tens of nanoseconds. Even though such speeds are superior to most other comparable memories that are currently commercially available, even greater speeds would certainly be desirable.
The present invention may address one or more of the problems set forth above.